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Intel Leaps 2-4 Years Ahead Of Samsung And TSMC On High-NA EUV Lithography After Producing Its 1 Millionth Test Wafer

The Hot Take: GOOD, we needed this.

The fates appear to have turned benevolent towards Intel, especially as its multi-year strategic pivots are now finally on the cusp of paying financial dividends, as evidenced by the chipmaker's rapidly expanding EMIB-T capacity as well as its hefty lead against Samsung and TSMC on high-NA EUV technology. UBS now believes Intel can easily meet MediaTek's growing TPU-related demand for EMIB-T advanced packaging, replete with the ability to package over 2 million substrates by 2028 According to UBS, the wider industry is becoming increasingly…

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Intel surpasses one million High-NA EUV wafers processed, outpaces the rest of the industry combined — company also trailblazing giant 6×12 photomasks to speed production and lower costs

The Hot Take: Intel is making headway fast to get back to the top of the manufacturers for sure.

Intel announced on Monday that it had processed more than one million 300-mm wafers using its High-NA EUV scanners, less than two and a half years after its first tool was assembled. For now, the company intends to use industry-standard 6-inch photomasks, which can expose 26×16.5 mm half-fields and therefore require field stitching for larger chips. However, Intel is also working on larger 6×12-inch photomasks that would enable High-NA EUV scanners to expose full 26×33 mm fields without stitching.One million High-NA wafersIntel's one million…

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Intel’s Defect Density Minimization For Its 14A Node Is Currently Tracking ~3-4 Quarters Ahead Of The 18A Node Trajectory, Indicating An Earlier Launch

The Hot Take: Very good news, ratchet up that heat in competition for TSMC & Samsung.

Intel is a bundle of positive tailwinds these days, especially in relation to its next-gen 14A chip fabrication process, as evidenced by an increasing likelihood of a firming order book for the process, and a defect density curve that is running ahead of the comparable trajectory for the current-gen 18A node. If Intel's 14A process simply follows the defect density curve trajectory of the current-gen 18A process from here onward, the chipmaker's next-gen process will likely be ready for its commercial debut by Q2 2028 For the benefit of those…

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Intel 14A defect density is dropping faster than the company expected — 'we have not seen this performance since 22nm,' says CFO

The Hot Take: Good, needed more than just for their own products but defense too.

Intel's confidence in its 14A (1.4nm-class) fabrication process is rising as defect density drops. The company's own design teams are at work developing products that will use the technology, while external customers are now asking about 14A volumes Intel can get them, according to David Zinsner, chief financial officer of Intel, who spoke at Deustche Bank's 2026 Technology Conference. The CFO went as far as saying that 14A is Intel's best process since 22nm technology from the 2010's. But while the comment is optimistic, there is a…

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Intel Rushes To Fill One Of Its Last Remaining Empty Clean Rooms Located Within Fab 38 In Israel Despite Geopolitical Risk And Lower Subsidies

The Hot Take: Filling capacity across the globe it appears. GOOD.

Intel is a hive of activity these days, so much so that it's now apparently rushing to fill its heretofore empty clean rooms while aggressively expanding capacity even in a location with relatively lower subsidies/tax credits and a much higher quantum of embedded geopolitical risk - Fab 38 in Israel. Hoffman Construction has updated its Fab 38 page to disclose 2026 as the wrap-up year of its contractual obligations, while a new Intel job vacancy for the Kiryat-Gat Site Master Planner has also opened up Back in July 2025, Intel had paused the…

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Intel Cracks The Encapsulation Wall Blocking Hyper-Large Chips, Pushing Advanced Packaging To 24x Reticle Size and Beyond

The Hot Take: Good, USA needs a strong Intel manufacturing.

Intel has overcome one big challenge that will lead to the creation of hyper-large chips beyond 12x reticle size through advanced packaging technologies. Intel Is Creating The World's Most Advanced & Largest Chips in the US at Its New Mexico "Rio Rancho" Facility, Leveraging Next-Gen Packaging Innovations Modern-day chips don't rely on a single piece of silicon, and instead utilize a range of silicon dies, interconnected together using the latest packaging solutions. The terminology used for such designs is chiplets, and chiplets were made…

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Intel Emerges as America’s Only Leading-Edge Chipmaker as RAMP-C Hands the Department of War Domestic 18A Production

The Hot Take: As it should be, given all of the other ones are own by foreign entities.

Intel has completed its RAMP-C program, which now aims to enable customers to move from test chips to domestic high-volume manufacturing. Intel RAMP-C Leads To Successful Development of a Strong "Design Enablement Infrastructure" Which Enables Commercial & Defense Customers To Design & Fabricate Chips Within the US Press Release: Intel Foundry has completed the Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) program. Launched in September 2021, the program supported development of domestic, leading-edge CMOS technology…

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Intel fortifies Foundry with an actual customer: Fortinet

The Hot Take: The more the merrier and helps Intel get back to track making and developing x86 CPUs. Hopefully GPUs too.

Fortinet on Tuesday revealed it will use Intel Foundry to fab its sixth-gen Security Processor (SP6), a nice win for Chipzilla's sputtering chipmaking biz. The chips feature dedicated accelerators designed specifically for the security and cryptographic operations required by modern hardware firewalls. The custom chips are one of Fortinet's defining features. Many cybersecurity hardware players build appliances around commodity hardware like x86 and Arm CPUs, but Fortinet prefers custom application-specific integrated circuits (ASICs). The two…

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TSMC’s CFO Admits US Fabs Cost Four To Five Times More Than Taiwan, Yet Doubles Down With $100B Bet

The Hot Take: Bitch and moan, better than paying the tariffs sir.

TSMC's CFO Wendell Huang shared last week that the firm is seeing strong demand from US customers. The executive's comments came after the Taiwanese firm's latest earnings report, which also saw it announce an additional $100 billion investment in the US. Huang outlined that TSMC's 3-nanometer facilities in the US should come online by the second half of next year and added that the costs of building facilities in the US were higher than in Taiwan. TSMC CFO Says US Fabs Cost Four To Five Times More To Build Than In Taiwan TSMC's latest $100…

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