The Hot Take: As it should be, given all of the other ones are own by foreign entities.
Intel has completed its RAMP-C program, which now aims to enable customers to move from test chips to domestic high-volume manufacturing. Intel RAMP-C Leads To Successful Development of a Strong "Design Enablement Infrastructure" Which Enables Commercial & Defense Customers To Design & Fabricate Chips Within the US Press Release: Intel Foundry has completed the Rapid Assured Microelectronics Prototypes - Commercial (RAMP-C) program. Launched in September 2021, the program supported development of domestic, leading-edge CMOS technology and manufacturing in the United States, establishing a foundation for expanded trusted domestic semiconductor manufacturing. “The collaboration between the DoW and Intel on the Trusted […]Read full article at https://wccftech.com/intel-emerges-as-americas-only-leading-edge-chipmaker-as-ramp-c-hands-domestic-18a-production/
The Hot Take: ASML needs competition, but I wasn't saying from China. LOL
According to The Information (paywalled), a state-backed Shanghai company has begun mass-producing China's first homegrown immersion DUV lithography machines, with about five units expected this year for SMIC, Hua Hong, and CXMT. Roughly 20 more units are expected in 2027. Tom's Hardware reports: The Information didn't name the manufacturer, but its sources described the operation as having pulled DUV development teams from several Chinese companies, one of them the state-backed startup Shanghai Yuliangsheng Technology. SMIC has been testing a Yuliangsheng immersion tool since September 2025. Most components in the new systems are domestic, though some critical parts still come from Japan, and delays at local suppliers have held back output this year.
[...] China accounts for around 20% of ASML's net sales this year, down from 33% in 2025, driven mainly by mainstream logic demand... Independent analysis from the AI Futures Project in June put commercial-scale Chinese immersion DUV in the mid-2030s, with ASML holding 98.7% of the immersion market. Qualifying the new machines for production lines could take many months, and they trail ASML's tools on performance and build quality. China's domestic EUV effort, which Reuters first reported as a working prototype in December, remains years away.
Read more of this story at Slashdot.
The Hot Take: USA domestic manufacturing is blowing up and saving Intel.
Intel Foundry might be heading into a big deal with NVIDIA, as the company is expected to offer packaging and wafer support for next-gen Feynman GPUs. NVIDIA Feynman GPUs Could Be Intel Foundry's Biggest Win To Date With Chipzilla Providing Both Packaging & Wafer Supply A deal between Intel and NVIDIA won't be a major surprise for those following our previous reports, but it is definitely a big win for Intel's Foundry business. Earlier this year, we reported that NVIDIA might be looking into Intel's upcoming process & advanced packaging technologies for its next-generation GPUs, codenamed Feynman. Well, according to […]Read full article at https://wccftech.com/intel-foundry-nvidia-feynman-gpu-wafer-packaging-deal/
The Hot Take: The more the merrier and helps Intel get back to track making and developing x86 CPUs. Hopefully GPUs too.
Fortinet on Tuesday revealed it will use Intel Foundry to fab its sixth-gen Security Processor (SP6), a nice win for Chipzilla's sputtering chipmaking biz. The chips feature dedicated accelerators designed specifically for the security and cryptographic operations required by modern hardware firewalls. The custom chips are one of Fortinet's defining features. Many cybersecurity hardware players build appliances around commodity hardware like x86 and Arm CPUs, but Fortinet prefers custom application-specific integrated circuits (ASICs). The two companies haven't said when the chips will enter production, much less what the SP6's speeds and feeds will entail, though we imagine it'll have a bit more pep than Fortinet's SP5 chips. The SP5 launched in 2023 and boasted support for layer 7 firewalling and IPsec VPN connectivity at speeds exceeding 30 Gbps. Throughput fell when advanced threat protection or SSL inspection was enabled, but Fortinet still claimed a speedy 4.3 Gbps and 3.3 Gbps, respectively. As you might have already figured out, Fortinet's SP line is designed primarily for smaller appliances like SD-WAN gateways, rather than larger datacenter-centric appliances built around its beefier NP and CP-series parts. While Intel couldn't offer much detail on the chip itself, we're told it will use the older Intel 4 process node rather than the leading-edge 18A process tech. Chipzilla also suggested Fortinet will draw on its experience in disaggregated semiconductor design and advanced packaging, which could mean a chiplet architecture with greater scalability. With so little detail, we can only speculate. Intel declined to say which technologies beyond Intel 4 the chip will use. The x86 giant also declined to comment on the availability of the product, noting only that "details regarding the Fortinet Security Processor 6 availability will be announced at a later date." While SP6 won't use the latest chipmaking tech, it will be built in an American fab by an American company, offering a level of supply chain security that remains difficult to find. If you want even remotely leading-edge silicon, Intel, Samsung, and TSMC are your only options. US-based production can still mean settling for a less advanced process, although TSMC's first Arizona fab has already begun churning out 4 nm silicon and Samsung aims to bring its new Texas plant online this year. Fortinet would not be the first to enlist Intel's manufacturing might for sensitive workloads. Under DARPA's HIVE program, the chipmaker built an eight-core, 528-thread processor with 1 TB/s silicon-photonics interconnects specifically to accelerate graph analytics workloads. But it doesn't stop at the DoD. Supply chain security is something Intel has leaned into as it has sought to reinvent itself from an integrated device manufacturer serving mainly itself, and occasionally the US government, into a full-fledged foundry ready to compete with Samsung and, ultimately, TSMC. In mid-2024, Uncle Sam awarded Intel $3 billion to establish a secure enclave for manufacturing chips for government agencies. Since then, the US government has taken a 9.9 percent stake in the American chip biz. ®
The Hot Take: Bitch and moan, better than paying the tariffs sir.
TSMC's CFO Wendell Huang shared last week that the firm is seeing strong demand from US customers. The executive's comments came after the Taiwanese firm's latest earnings report, which also saw it announce an additional $100 billion investment in the US. Huang outlined that TSMC's 3-nanometer facilities in the US should come online by the second half of next year and added that the costs of building facilities in the US were higher than in Taiwan. TSMC CFO Says US Fabs Cost Four To Five Times More To Build Than In Taiwan TSMC's latest $100 billion announcement will expand the […]Read full article at https://wccftech.com/tsmcs-cfo-admits-us-fabs-cost-four-to-five-times-more-than-taiwan-yet-doubles-down-with-100b-bet/
The Hot Take: ASML's monopoly needs get challenged, but not sure if Quantum will just make them invalid. We'll have to wait and see I guess.
Intel has entered high-volume manufacturing using ASML's High NA extreme ultraviolet (EUV) lithography technology for a subset of its Intel Core Ultra Series 3 "Panther Lake" processors, becoming the first company to ship high-volume logic products manufactured with the technology. ASML announced the milestone in an official press release on Wednesday, July 15, confirming that Intel Foundry is running the qualified High NA layers on its Intel 18A process node in Oregon.Go deeper with TH Premium: Chipmaking(Image credit: tsmc)A deeper look at the chipmaking supply chainTSMC's $165 billion U.S. investments examinedChina reportedly reverse-engineers EUV toolChina bets on DUV, as EUV blockade reshapes chipmakingAccording to ASML, Intel is using High NA EUV to pattern selected Intel 18A layers, with products already shipping to customers at yields matched to those achieved on ASML's existing NXE EUV platform. These layers are dual-qualified, meaning the same layer can be exposed on either an existing 0.33 NA NXE scanner or a 0.55 NA EXE scanner, with the resulting wafers being interchangeable.High NA EUV has long been viewed as the successor to today's EUV lithography, promising to extend semiconductor scaling by enabling manufacturers to print smaller, denser circuit patterns that are becoming difficult to achieve with existing tools. Until now, the platform had been confined to R&D work. ASML’s announcement marks the first time High NA EUV has been used to produce and ship a high-volume commercial logic product. Panther Lake, built on the Intel 18A manufacturing process, is spearheading this transition. Rather than replacing the company's entire lithography flow, Intel is applying High NA EUV to specific layers while the remainder of the chip continues to be manufactured using conventional lithography. High NA EUV builds on the same 13.5-nanometer extreme ultraviolet light used by today's scanners but increases the optical system's numerical aperture (NA) — how much light a lens system can collect and focus onto a silicon wafer — from 0.33 to 0.55. The higher value resolves finer features in a single exposure, allowing chipmakers to print smaller patterns with greater precision and process control.This increased resolution is expected to reduce reliance on complex multi-patterning techniques for some of the industry's most demanding layers, thereby simplifying manufacturing and improving feature fidelity. In the long term, these capabilities are expected to support higher transistor densities and improved performance in future processors, particularly as AI workloads continue driving demand for increasingly advanced semiconductor technologies."With increased resolution and better process control, the introduction of High NA EUV marks a substantial development in semiconductor lithography," said ASML President and CEO Christophe Fouquet. "We are proud to play a role in enabling the smaller, denser patterning that will accelerate advancements in AI and other emerging technologies." Intel and ASML have been working towards this milestone for several years. In 2024, Intel completed installation of one of the industry's first commercial High NA EUV lithography systems, the TWINSCAN EXE:5000, at its Hillsboro, Oregon, research and development facility. The company later became the first to qualify ASML's second-generation TWINSCAN EXE:5200B, which increases wafer throughput and overlay accuracy while incorporating an improved EUV light source over its predecessor.While the announcement represents High NA EUV's commercial debut, it does not mean Panther Lake is manufactured entirely using the new lithography platform. Instead, Intel has qualified High NA for selected layers, an approach that mirrors how new lithography generations are typically introduced into advanced semiconductor production before broader adoption across future nodes.Intel Foundry Executive Vice President and General Manager Naga Chandrasekaran said that qualifying the High NA process option on selected Intel 18A product layers enables the company's existing tool fleet to deliver higher manufacturing output while providing flexibility for future process technologies.Panther Lake itself is not a future product. Intel launched Core Ultra Series 3 at CES on January 5, 2026, opened preorders the following day, and put systems on shelves globally from January 27. The Core Ultra X9 378H followed in April alongside the value-tier Core Series 3, code-named Wildcat Lake, and the handheld-focused Arc G3 parts arrived on May 28.The announcement’s statement that the product is shipping to customers refers to wafer flow from the fab into the supply chain, rather than to a product launch. ASML says the two companies will continue working on High NA readiness, with the flexibility to incorporate the technology into future nodes based on customer needs — most immediately, Intel 14A, which Intel has designed to use High NA on a set of its tightest-pitch layers.
Intel is reportedly making a significant change to the manufacturing strategy for its upcoming Nova Lake processor family by shifting the majority of compute tile production back to Intel Foundry.
The Hot Take: Makes sense, especially if China takes Taiwan....
According to the Wall Street Journal (paywalled), Apple agreed to use Intel's U.S. chipmaking plants after White House officials pressured Tim Cook during tariff-relief talks last summer. MacRumors reports: In August 2025, Apple CEO Tim Cook was in Washington to lobby the Trump administration to drop its proposed 100 percent tariff on semiconductor imports -- a levy that would have raised costs across Apple's product line. Apple reportedly secured an exemption after pledging to invest hundreds of billions of dollars in the U.S., although many of those investments were already planned. During the meetings, president Trump and commerce secretary Howard Lutnick are said to have urged Cook to use Intel's fabrication plants to make some of Apple's chips. The link between the tariff talks and the Apple-Intel deal had not been previously reported.
Almost a year later, Trump announced via his Truth Social platform that Apple would begin using Intel-made chips in some products. "We need to design and build our Chips right here in America," the president posted. The news sent Intel shares to record highs. According to a person familiar with the negotiations cited by the WSJ, Apple plans to have Intel make chips for both Mac laptops and iPhones. The report doesn't say which chips or in what volume, and Apple is expected to remain reliant on Taiwan Semiconductor Manufacturing Company, or TSMC, for the majority of its custom silicon.
Read more of this story at Slashdot.
The Hot Take: New Micro-FAB? Jim Keller involvement, interesting.
Atomic Semi, the semiconductor tooling startup founded by chip architect Jim Keller and DIY fabrication pioneer Sam Zeloof, has rebranded as Fab2 and moved its operations to Texas, according to the company's new site at fab2.com. The rebrand recasts the company around the idea they're calling a "fab fab," a factory that mass-produces small semiconductor fabs and the tools inside them.Fab2 designs and builds every tool in its fabs in-house, from pumps, valves, and gas lines to lithography and the vacuum chambers that house it. The company assembles those components into machines, the machines into complete fabs, and then aims to mass-produce the fabs themselves. It pairs the hardware with Studio, an in-browser, collaborative EDA tool for layout, schematic, and simulation work, previously branded as Atomic Studio.Rather than moving 300mm wafers through ginormous production lines, Fab2 targets small, software-defined fabs that pattern chips far smaller than a wafer and turn prototypes around in hours. Zeloof built the concept's proof point as a teenager, fabricating lithographic chips in his parents' garage down to roughly 300nm features before co-founding this company with Keller in 2022.The method's main constraint, however, is throughput. Electron-beam lithography writes patterns directly rather than projecting them through a mask, which makes it slow: a single patterning step on a small chip can take far longer than an EUV scanner needs to expose an entire 300mm wafer. That's a big tradeoff that only really suits prototyping and low-volume runs rather than high-volume production at commercial foundries.Fab2 now operates three sites: a 120,000 square foot facility in Austin serves as the new headquarters for research and production, a 30,000 square foot site in Lockhart houses the "fab fab" itself, and the original 25,000 square foot "garage fab" remains in San Francisco. Fab2 said it shifted its hiring focus to Texas after four years in California, and Tracxn lists the company at around 84 employees as of May 2026. The startup raised a reported $15 million seed round in 2023, led by the OpenAI Startup Fund, at a valuation of about $100 million, with angel backing from Naval Ravikant, Nat Friedman, and Fred Ehrsam.In moving to Texas, Fab2's model of many small, printable fabs now sits beside the likes of Tesla and SpaceX, which announced Terafab back in March, a single Austin megafab targeting a terawatt of annual compute at a cost of up to $119 billion. The contrasting businesses are clearly not competitors; Fab2 sells small fabs and prototyping speed, while Terafab is built for high-volume AI. But they represent competing answers to the same question of how the U.S. should expand its chipmaking capacity — consolidate everything in massive manufacturing campuses, or distribute production across many small, replicable fabs?
The Hot Take: Intel Ramping things up to play catch up and win volume from TSMC.
Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.Go deeper with TH Premium: Chipmaking(Image credit: tsmc)A deeper look at the chipmaking supply chainTSMC's $165 billion U.S. investments examinedChina reportedly reverse-engineers EUV toolChina bets on DUV, as EUV blockade reshapes chipmakingEarlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch × 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies — such as Intel's 18A, 18A-P, 14A, and more advanced — that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.(Image credit: Intel)Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop — which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial. Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.(Image credit: Intel)"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.IntelIntel