The Hot Take: Intel Ramping things up to play catch up and win volume from TSMC.
Intel this week initiated expansion of its Bowers Campus in Santa Clara, California, in a bid to produce more photomasks (reticles) in the U.S. The company intends to build a new manufacturing facility and a new utility building at the site, which will reinforce the site's position as a key producer of photomasks for Intel.Go deeper with TH Premium: Chipmaking(Image credit: tsmc)A deeper look at the chipmaking supply chainTSMC's $165 billion U.S. investments examinedChina reportedly reverse-engineers EUV toolChina bets on DUV, as EUV blockade reshapes chipmakingEarlier this year Intel obtained approval to build a new 107,000 square feet (9,940 square meters) manufacturing facility with Class 1 cleanroom at its Bowers Campus, and this week it formally began construction on the expansion, which it kicked off at a ceremony attended by its top executives and Santa Clara mayor Lisa Gilmor. The new facility will be able to write 6-inch Ă 6-inch photomasks both for DUV and EUV layers and a variety of nodes (from 32nm down 1.4nm-class), though the primary focus of the facility is to produce reticles for leading-edge process technologies â such as Intel's 18A, 18A-P, 14A, and more advanced â that rely on advanced DUV, EUV and eventually High-NA EUV tools and require more advanced photomasks, such as those that feature extremely dense patterns and use curvilinear optical proximity correction (OPC) with curved geometric shape.(Image credit: Intel)Intel is one of a few leading chipmakers in the world that still maintains a world-class mask writing shop â which is important, as every advanced product requires hundreds of masks, and every mask revision directly affects production schedules. In addition, producing masks in-house is getting particularly important when it comes to reticles for EUV layers as EUV tools tend to damage masks over time (despite usage of protective pellicles), so having the ability to make new masks in a short amount of time is crucial. Furthermore, Intel is the only semiconductor producer to make its own tools for photomasks writing at its IMS Nanofabrication subsidiary. Historically, reticles were patterned using a single e-beam tool, which was slow. By contrast, IMS produces multi-beam mask writers (MBMWs) that project 262,144 independently programmable electron beams simultaneously, which increases throughput by orders of magnitude at a nanometer-scale placement accuracy.(Image credit: Intel)"Santa Clara has been home to some of Intel's most important manufacturing innovations for decades," said Dr. Frank Abboud, VP Intel Foundry & GM of Intel Mask Operations. "By expanding the Bowers campus mask operations, we're strengthening a critical capability that supports advanced process technology production around the world and reinforces Intel Foundry's commitment to advancing U.S. semiconductor manufacturing leadership."Intel's Bowers Campus in Santa Clara has been dedicated to mask production since 1986. The site forms the company's primary mask manufacturing infrastructure supporting together with the company's facility in Hillsboro, Oregon. Production of non-critical masks has historically been outsourced, though we do not know whether the company still does that.IntelIntel
The Hot Take: Samsung playing catch up and hopefully over take TSMC? Only time will tell.
Korean chip manufacturing giant Samsung is developing simulation technologies for lithography that rely on quantum computing and artificial intelligence, suggests a report from the Korean press. The technology will be used to run simulations of the first stage of the chip manufacturing process, and Samsung will also rely on artificial intelligence to streamline the process. Through the technology, the firm aims to reduce the time and cost of the lithography and etching processes. Samsung Is Developing Algorithms To Boost Its Photolithography, Say Sources In the semiconductor manufacturing process, lithography is the first and most important step. It involves high-end machines, [âŚ]Read full article at https://wccftech.com/samsung-chases-tsmc-with-quantum-powered-chipmaking-as-ai-reshapes-the-most-critical-step-in-fabrication/
The Hot Take: Oh so the Ultra series aren't just crap then? /smh
It's curious to call this one a leak, exactly, since the original source is direct from AMD and live on the web, but here we go: AMD's Vishal Badole submitted a patch for the Linux Kernel that he describes as adding support for "a Low Power core type, in addition to the existing Performance and Efficiency types." That's pretty clear-cut.
Now,
A new class-action lawsuit filed in California accuses SK hynix, Samsung, and Micron of coordinating DRAM production to artificially restrict supply and maintain elevated prices for consumer memory products.
The Hot Take: About time. I've been saying they should have one for a while.
The big story in computing these days is how an ongoing shortage of RAM (dubbed RAMageddon or the RAMpocalypse) has led to massive increases in hardware costs. The conventional explanation of the situation has been that shortages have been driven by the widespread construction of AI data centers. However, a new lawsuit (Garciaguirre et al. v. Samsung Electronics Co., Ltd., et al.) filed against RAM manufacturers Samsung, SK Hynix, and Micron, alleges that these companies are exploiting market conditions to artificially inflate prices.
The Hot Take: Interesting, Risc-V shop from rockstar architect Jim Keller.
Jim Keller isn't bothered by Cerebras's recent IPO and says that he welcomes it, but Tenstorrent will still beat them on everything. Tenstorrent CEO, Jim Keller, Signals Deal With Intel or Qualcomm While Promising To Beat Cerebras "on everything" Tenstorrent recently introduced its latest BlackHole Galaxy server, a system with which it can disrupt the entire AI segment, with performance levels that crush the competition. We covered the announcement last month when the company demoed its Blackhole server undercutting a NVIDIA GB300 with up to five times better TCO. Keller Accepts The Challenge To Beat NVIDIA, Cerebras & Others At [âŚ]Read full article at https://wccftech.com/jim-keller-cerebras-ipo-was-helpful-tenstorrent-to-beat-them-on-everything/
The Hot Take: I just hear Tim Allen in my head from tool time.
Intel is expected to push the boundaries on power draw with its upcoming Nova Lake series processors, which will rival the best CPUs. According to newly leaked information, the flagship 52-core desktop variant is expected to feature a dual-compute tile architecture with a massive PL2 limit of 474W. The information was shared by LC Tech Leaks and confirmed by Jaykihn, who has a pretty solid track record with Intel hardware.PL2, or Power Limit 2, represents the maximum power a CPU can draw during short boost periods. That said, a PL2 target of 474W remains quite demanding, although a previous rumor suggests Intel may also have a PL4 emergency power limit over 700W. It is important to note that these power limits may only apply to the top-end models with the dual-tile architecture.Additionally, the leak also sheds light on the upcoming platform, including the previously rumored LGA1954 socket. We already know that Nova Lake-S will require a new generation of motherboards. Motherboard vendors are expected to classify their boards by sustained PL1 power levels, with configurations for 35W, 65W, 125W, and 175W CPUs. Enthusiast-grade motherboards, likely the Z990 series, are also rumored to feature three EPS 8-pin CPU power connectors instead of the traditional two. While vendors will have the option to include a third connector, its primary purpose would be to support extreme overclocking and would not affect the CPU's rated performance profile.The upcoming Nova Lake-S lineup is expected to carry the âCore Ultra 400Sâ moniker and will be Intel's biggest desktop CPU overhaul in years. Weâve previously reported leaked specifications indicating configurations ranging from 6 to 52 cores, with support for DDR5-8000 memory. The flagship 52-core model is expected to feature 16 performance cores, 32 efficiency cores, and a new Big Last Level Cache (bLLC) design to take on AMD's 3D V-Cache gaming dominance. The company is also rumored to introduce integrated Xe3 graphics, Thunderbolt 5, PCIe 5.0 connectivity, and an upgraded NPU for AI workloads.While these specifications are unconfirmed, it is clear that Intel is targeting substantial gains in gaming, multi-threaded performance, and overall platform capabilities with its next-gen processors.
The Hot Take: We'll see how long before they go to Intel because TSMC is filled up in Arizona FABs.
Nvidia will stay TSMCâs biggest customer in 2027, but AMDâs EPYC Venice could pinch the CPU bragging rights.
TSMC is seeing rising demand for 2.5D advanced packaging as CPUs become more important in the agentic AI bunfight. Apparently, GPUs alone are no longer enough to feed the machine.
Morgan Stanley reckons Nvidia will remain TSMCâs largest CoWoS customer in 2027. TSMC is expected to reach wafer capacity of 200,000 wafers a month that year.
Nvidia is using TSMCâs CoWoS packaging for two main product families. CoWoS-L is for AI GPUs such as Blackwell and Rubin, while CoWoS-R is for Vera CPUs.
CoWoS-L capacity is expected to hit about 910,000 units, up 40 per cent year on year. Vera shipments are expected to double, which would help Nvidia lift data centre revenue by 52 per cent.
Morgan Stanley said:âNvidia uses TSMCâs CoWoS-L as the single source for all its AI GPU products (e.g. Blackwell and Rubin). Its 2027 CoWoS-L consumption could reach ~910k, up ~40 per cent year on year. Strong CoWoS-R bookings by Nvidia suggest room for AI GPM products (such as doubling). Taken together, we estimate Nvidiaâs 2027 forecast for Nvidiaâs data centre revenue to rise 52 per cent year on year.â
Nvidia has been pivoting harder into CPUs to claw back China revenue after GPU restrictions. Several customers have shown interest in Vera CPUs.
The company has hand-delivered the first Vera CPUs to Anthropic, OpenAI, SpaceX and Oracle. Nothing says âagentic AI eraâ like an expensive chip being passed around the usual suspects.
The problem for Nvidia is that AMD is not politely standing at the back. Its next-generation EPYC Venice platform is already in volume production at TSMC.
Venice is based on AMDâs upcoming Zen 6 architecture and is expected to deliver better performance and efficiency. It targets both AI and HPC, while Vera is being pitched squarely at agentic AI.
Morgan Stanley projects Nvidiaâs Vera CPUs could reach 5.75 million units by 2027. AMDâs EPYC Venice, though, could reach 6.75 million units in 2027. That is 17 per cent more than Vera and 5.4 times its expected 2026 volume.
âBased on our CoWoS consumption forecasts, Nvidiaâs 5nm Vera CPU could grow to 5.75mn units in 2027, while AMDâs 2nm Venice CPU may reach 6.75mn units in 2027 vs. ~1.25mn in 2026,â the beancounters said.
AMD has another advantage on paper, with Venice using TSMCâs advanced 2-nanometre process. Vera is based on a 3-nanometre process. The real headache for both companies may not be each other. It is custom silicon, where the cloud crowd is deciding that buying chips off the shelf is for the riffraff.
OpenAI, Google, Amazon and others are either talking up custom chips or already building them. That turns the AI supply chain into a fight between outside suppliers and in-house silicon vanity projects.